1- Job Title: Emulation Engineer 

·         Experience in Verilog, VHDL and System Verilog RTL understanding and writing testbench. 

·         Compilation for emulation - front-end and Back-end flow. 

·         Strong RTL Debug skills on Emulation/Simulation using Triggers, SVA assertions.

·         Knowledge on Verdi tool is preferred. 

·         Competency in Scripting language such as Python, TCL 

·         Pre-Si validation & Debug.