We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a passionate engineer with a strong foundation in analog design, eager to tackle complex challenges and drive innovation in the semiconductor industry. Your expertise in CMOS processes and deep submicron technologies sets you apart, and you thrive in environments where precision and performance are paramount. You possess a keen understanding of circuit design, layout methodologies, and mixed-signal circuitry, and you are always seeking ways to optimize and improve. You are familiar with industry standards like JEDEC for DDR interfaces and understand the nuances of DDR timing, On-Die Termination (ODT), and SDRAM functionality. You approach assignments with a commitment to quality and efficiency, balancing technical rigor with practical execution. Collaboration is second nature to you; you communicate effectively with cross-functional teams and are adept at explaining complex concepts in both written and verbal formats. You are motivated by the opportunity to contribute to high-impact projects that shape the technology landscape, and you value continuous learning and professional growth. Whether you’re mentoring junior engineers or spearheading innovative solutions, you bring a collaborative spirit and a relentless drive for excellence. Your attention to detail, problem-solving skills, and adaptability ensure you deliver results that exceed expectations. If you’re ready to work on cutting-edge silicon IP and empower the next generation of smart devices, Synopsys is the place for you.
What You’ll Be Doing:

• Designing DDR I/O circuits for high-performance silicon IP, ensuring compliance with industry standards and customer requirements.
• Developing and optimizing analog/mixed-signal circuit architectures, focusing on performance, power, and area efficiency.
• Executing circuit design tasks using advanced CMOS processes and state-of-the-art layout methodologies.
• Collaborating with internal development teams to integrate analog blocks into ASIC and SoC designs.
• Assessing and resolving issues related to deep submicron process technologies, including ESD concepts and reliability concerns.
• Validating and verifying designs through simulation and analysis, maintaining rigorous product quality standards.
• Documenting design approaches and communicating progress and results to stakeholders.
The Impact You Will Have:

• Accelerate the integration of advanced DDR interfaces into customer SoCs, enabling differentiated products to reach market faster.
• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.
• Drive innovation in analog and mixed-signal circuit design, influencing industry standards and best practices.
• Reduce development risks and ensure robust design solutions for next-generation applications.
• Support cross-functional teams by providing technical expertise and insights, fostering collaboration and knowledge sharing.
• Contribute to the continuous improvement of design methodologies and workflows, ensuring Synopsys remains at the forefront of technological advancement.
What You’ll Need:

• BTech/MTech in Electrical Engineering or related field; MTech+3 years or BTech+5 years of relevant experience.
• Strong knowledge of CMOS processes and deep submicron technology challenges.
• Hands-on experience with analog/mixed-signal circuit design and layout methodologies.
• Familiarity with ASIC design flow and integration of analog blocks.
• Understanding of JEDEC DDR interface standards, DDR timing, ODT, and SDRAM functionality.